Vivanco 10-100MB FAST ETHERNET SWITCH 5 PORTS - PROGRAMMING Spezifikationen Seite 19
- Seite / 82
- Inhaltsverzeichnis
- LESEZEICHEN
- Physical Layer Transceiver 1
- 1.4 Functional Block Diagram 2
- 3 Device Comparison 4
- 4.1 Pin Layout 5
- 4.2 Package Pin Assignments 6
- 4.4 Mac Data Interface 6
- 4.5 Clock Interface 7
- 4.6 LED Interface 8
- 4.8 Reset and Power Down 8
- 4.9 Strap Options 8
- 4.11 Special Connections 10
- 4.12 Power Supply Pins 10
- 5 Specifications 11
- 5.5 DC Specifications 12
- 5.6 AC Timing Requirements 13
- DP83848C 14
- DP83848I 14
- DP83848VYB, DP83848YB 14
- Specifications 17 17
- Submit Documentation Feedback 17
- Specifications 19 19
- Specifications 21 21
- Specifications 23 23
- 6 Detailed Description 26
- 6.2 Functional Block Diagram 27
- 6.3 Feature Description 28
- 6.3.1 Auto-Negotiation 28
- Detailed Description 29 29
- 6.3.2 Auto-MDIX 30
- 6.3.3 LED Interface 30
- 6.3.4 Internal Loopback 32
- 6.3.5 BIST 32
- 6.3.6 Energy Detect Mode 33
- 6.4 Device Functional Modes 33
- 6.4.1 MII Interface 33
- 6.4.2 Reduced MII Interface 34
- 6.4.5 PHY Address 36
- 6.4.7 Reset Operation 38
- 6.5 Programming 39
- 6.5.1 Architecture 39
- Detailed Description 41 41
- Detailed Description 43 43
- SD = (UD ⊕ N) (1) 44
- UD = (SD ⊕ N) (2) 44
- Detailed Description 45 45
- Detailed Description 47 47
- 6.6 Memory 48
- 6.6.1 Register Block 48
- Table 6-8. Register Table 49
- 7.1 Application Information 68
- 7.2 Typical Application 68
- 7.2.1 Design Requirements 68
- 7.2.3 Application Curves 75
- 7.3 Layout 76
- 7.3.1 Layout Guidelines 76
- 7.3.2 Layout Example 78
- PACKAGE OPTION ADDENDUM 80
- IMPORTANT NOTICE 82
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